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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 may 1994 integrated circuits philips semiconductors saa2013 adaptive allocation and scaling for pasc coding in dcc systems
may 1994 2 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 features wide operating voltage range: 2.7 to 5.5 v low power consumption: 13 mw; 3.0 v low power decode mode: 1 mw; 5.0 v sleep mode for low power and low electromagnetic interference (emi) sophisticated allocation algorithm optimum sound quality three-wire l3 bus microcontroller interface stereo or 2-channel mono recording small surface mounted package (qfp; sot307). general description the saa2013 performs the adaptive allocation and scaling function in the precision adaptive sub-band coding (pasc) system. it is not required in playback only applications, and is only used during recording. to complete the pasc processor, a saa2003 stereo filter and codec is required. ordering information note 1. when using reflow soldering it is recommended that the dry packing instructions in the quality reference pocketbook are followed. the pocketbook can be ordered using the code 9398 510 34011. type number package pins pin position material code SAA2013H 44 qfp (1) plastic sot307-2
may 1994 3 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 block diagram fig.1 block diagram. handbook, full pagewidth mgb355 v dd2 v dd1 v dd3 14 24 40 6 25 44 saa2013 microcontroller bus 3 4 5 l3modem l3clkm l3datam control and sync compensation delay 39 sfc bus allocation and scale factor computation 37 36 35 34 fs256 fdir freset fsync fdai 32 31 30 26 33 9 10 11 l3modec l3clkc l3datac 22 21 20 nodone resol0 resol1 v ss2 v ss1 v ss3 fdcl fdws sleep clk24 23 reset fdao
may 1994 4 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 pinning symbol pin description type test10 1 test input; connect to v ss i test11 2 test input; connect to v ss i l3modem 3 microcontroller interface mode input i l3clkm 4 microcontroller interface clock input i l3datam 5 microcontroller interface data 3-state input/output i/o v ss1 6 supply ground - test12 7 test output; do not connect o test13 8 test output; do not connect o l3modec 9 codec interface mode output o l3clkc 10 codec interface clock output o l3datac 11 codec interface data 3-state input/output i/o test1 12 test output; do not connect o test2 13 test output; do not connect o v dd1 14 supply voltage - test3 15 test mode input; connect to v dd i test4 16 test mode input; connect to v dd i test5 17 test input; connect to v ss i test6 18 test input; connect to v ss i test7 19 test input; connect to v ss i nodone 20 nodone state selection input; connect to v dd i resol0 21 resolution selection 0 input i resol1 22 resolution selection 1 input i reset 23 reset input; active high i v dd2 24 supply voltage - v ss2 25 supply ground - clk24 26 24.576 mhz clock input i lowpwr 27 low power decode select input i por 28 power on reset input i test8 29 test input; connect to v ss i sleep 30 sleep mode select input i fdws 31 ?ltered data word select i fdcl 32 ?ltered data clock i fdao 33 ?ltered data output o fdai 34 ?ltered data input i fsync 35 sub-band synchronization on ?ltered i 2 s bus i freset 36 reset signal input from saa2003 i fdir 37 ?ltered data direction input i test9 38 test input; connect to v ss i fs256 39 system clock input; 256 sample frequency (f s )i v dd3 40 supply voltage -
may 1994 5 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 n.c. 41 not connected - n.c. 42 not connected - n.c. 43 not connected - v ss3 44 supply ground - symbol pin description type fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 fdao fdcl fdws sleep test8 v clk24 reset ss2 v dd2 n.c. n.c. n.c. ss3 dd1 test9 fdir freset fsync fdai v v test10 test11 l3modem l3clkm l3datam l3modec l3clkc l3datac saa2013 test1 resol0 resol1 mgb356 ss1 v test12 test13 por lowpwr fs256 test2 test7 test6 nodone test5 test4 test3 dd3 v
may 1994 6 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 functional description handbook, full pagewidth mbd620 tape drive processing dac tda1305 adc saa7366 analog output digital audio i/o tda1315 iec958 analog input audio in/out pasc processor i s 2 l r l r sfc3 saa2003 stereo filter codec adas3 saa2013 adaptive allocation filtered i s 2 sub-band i s 2 baseband drp saa2023 or saa3323 drive processor ram 41464 buffer 64k x 4 rdamp tda1380 read amp. wramp tda1381 write amp. fixed head tape capstan drive speed control mechanics drivers analog cc l output analog cc r output system microcontroller system control search data detect switch fig.3 dcc system block diagram.
may 1994 7 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 pasc processor the pasc processor is a dedicated digital signal processor (dsp) engine which efficiently codes digital audio data at a bit rate of 384 kbits/s without affecting the sound quality. this is achieved using an efficient adaptive data notation and by only encoding the audio information which can be heard by the human ear. the audio data is split into 32 equal sub-bands during encoding. for each of the sub-bands a masking threshold is calculated. the samples from each of the sub-bands are included in the pasc data with an accuracy that is determined by the available bit-pool and by the difference between the signal power and the masking threshold for that sub-band. in decode, the sub-band signals are reconstructed into the full bandwidth audio signal. the stereo filter codec performs the splitting (encoding) and reconstruction (decoding), including the necessary formatting functions. during encoding, the adaptive allocation and scaling circuit calculates the required accuracy (bit allocation) and scale factors of the sub-band samples. decode/encode control selection of decode or encode is controlled using freset and fdir. freset causes a general reset. the fdir signal is sampled at the falling edge of the freset signal to determine the operation mode. when fdir is high, saa2013 is in decode mode. when fdir is low the saa2013 is in encode mode. see fig.4. fig.4 fdir and freset timing. handbook, full pagewidth t h freset fdir t su t h mgb357 reset when used with low-power mode disabled (lowpwr = v ss ), and with the sleep input low, saa2013 is reset if the reset pin is held high for at least 5 periods of the clk24 clock, see fig.5. saa2013 defaults to decode mode. when in low-power mode, the reset pin is disabled. sleep mode sleep mode is entered by taking the sleep input high with the lowpwr pin connected to v ss ; clk24 and fs256 are stopped internally to the saa2013, the 3-state buffers will have a high impedance, and outputs will freeze in the same state as just before the sleep mode became active (clocks stopped). to come out of sleep mode, the sleep input must be taken low again. to clear data present from before sleep was entered, this should be followed by a reset, see fig.5.
may 1994 8 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 fig.5 sleep and reset timing. handbook, full pagewidth mgb358 t d t h sleep reset clk24 low-power decode mode low-power decode mode is made available by connecting the lowpwr pin to v dd . with lowpwr = v dd , low-power decode mode is entered 9 cycles of clk24 after the sleep input is taken high. in low-power decode mode, the l3 bus connections are connected straight trough the saa2013, which is effectively bypassed. the compensation delay connection between pins fdai and fdao is no longer needed by the saa2003, and clk24 and fs256 are stopped internally to the saa2013. to get out of low-power decode mode, it is necessary to take sleep low, fdir low, and freset high (in a normal application taking fdir low and freset high can be achieved by setting saa2003 into encode mode), saa2013 then performs an internal reset, and defaults to normal decode mode. the reset pin does not reset the circuit from low-power decode mode. power-on reset (por) when low-power decode mode is enabled (lowpwr = v dd ), a power-on reset circuit is required to ensure that the internal clocks are connected correctly at power-on. a suitable circuit is shown in fig.6. this circuit will correctly reset the internal clock connection provided that the nominal value of the v dd supply is reached within 40 ms at power-on. encode mode in encode mode the saa2013 receives sub-band filtered samples from saa2003 on the fdai pin. the saa2013 has to collect a complete frame of sub-band data before the allocation and scale factor information can be calculated. so that the allocation and scale factor information is available in the same time frame as the audio samples at the output, the sub-band filtered samples are delayed by 480 fdws periods. one fdws period is equal to where f s is the audio sample rate of 32, 44.1 or 48 khz. the delayed samples are passed to the codec part of saa2003 on the fdao pin. handbook, halfpage mgb359 v dd 150 w k m 1 f por v ss v dd v ss fig.6 por circuit. 1 f s --- -
may 1994 9 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 for each sub-band frame, saa2013 calculates the allocation and scale factor index information required by the saa2003. in order to synchronize the codec part of saa2003, saa2013 frequently requests status information from the codec. it monitors sample frequency, emphasis information and stereo mode, and uses the ready-to-receive bit of the codec to determine when to transfer information. decode mode in decode the saa2003 will transfer samples from fdai to fdao with a delay of 480 fdws periods. settings and status information can be sent to saa2003 via saa2013, but the saa2013 does not itself act on this information. transfer of this information is automatically synchronized to the ready-to-receive bit of saa2003 by saa2013. audio sample resolution section the saa2013 is designed for operation with audio input sources of 14, 15, 16 or 18-bit resolution. for optimum audio performance the bit allocation algorithm of the saa2013 can be varied to suit the bit resolution of the audio source. this is done with the pins resol0 and resol1 as shown in table 1. table 1 resolution set by pins resol0 and resol1. resolution resol0 resol1 16 bits 0 0 18 bits 0 1 14 bits 1 0 15 bits 1 1 filtered data interface the filtered data interface signals are given in table 2. table 2 filtered data interface signals. pin input/output function frequency fdws input ?ltered data interface word select f s fdcl input ?ltered data interface bit clock 64f s fdai input ?ltered data input - fdao output ?ltered data output - fsync input ?ltered data sub-band synchronization - the filtered data interface transfers sub-band filtered samples between the stereo filter codec saa2003 and saa2013. the interface is similar to a normal i 2 s interface, consisting of clock (fdcl), data (fdai/fdao) and word select lines (fdws), except that the samples sent represent signals divided into 32 sub-bands. one frame of data consists of 12 samples from 32 sub-bands for both left and right channels, i.e.: 768 audio samples. each audio sub-band sample is represented by a 24-bit twos complement number. the order in which the samples are sent is shown in table 3. for two channel mono, the order is the same, but with channel 1 samples in the place of left and channel 2 samples in place of right. table 3 order of samples. the signal fsync is used between each pasc frame to indicate the sending of samples for sub-band 0 (fig.7). sub-band 001122...3131 channel l r l r l r ... l r sample 000000...00 111111...11 222222...22 ........... ........... 11 11 11 11 11 11 ... 11 11
may 1994 10 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 fig.7 filtered interface format. h andbook, full pagewidth left right l r l r l r l r l r 31 0 1 31 0 32 bits t d3 cl t ch t t d4 t c t su1 t h1 fdcl fdao fdai fdws fsync sub-band fdws fdcl fdws channel fsync timing mgb360 1 bit 23 22 21 20 7 bit 0 1 control interfaces two 3-wire control interfaces are provided (referred to as l3 interfaces). one is connected to the system microcontroller (l3modem, l3clkm, l3datam where m represents microcontroller), the other to saa2003 (l3modec, l3clkc, l3datac where c represents codec). in general, control data is passed between saa2003 and the microcontroller via saa2013. this ensures that the microcontroller is buffered from the time-critical saa2013 to saa2003 interface during encode. the saa2013 does not interpret the data from the microcontroller interface. status information from the codec is interpreted to ensure that saa2013 quickly acts upon the status of saa2003. the l3 bus operation is shown in fig.8. there are three modes: 1. address. 2. data. 3. halt. each interface operates as either a master or a slave, where the master provides l3clk and l3mode. for the microcontroller to saa2013 interface, the microcontroller is the master. for the saa2013 to saa2003 interface, saa2013 is the master.
may 1994 11 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 handbook, full pagewidth l3mode l3clk l3data 01234567 mgb361 fig.8 l3 bus operation; address mode. handbook, full pagewidth l3mode l3clk l3data 01234567 mgb362 fig.9 l3 single byte transfer. handbook, full pagewidth l3mode l3clk l3data 8 9 10 11 12 13 14 15 mgb363 01 2 3 4 5 6 7 fig.10 l3 bus two byte transfer.
may 1994 12 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 a ddress mode address mode is entered by the master pulling l3mode low. this causes the l3data line to act as an input on the slave, and 8 bits of address data are clocked into the slave. if the slave recognizes the address, it will set-up its internal state based on the 2 least significant bits (lsbs) of the address. the slave than expects to send status data or receive control data. the addresses for saa2013 are shown in table 4. table 4 saa2013 addresses. the interface may be reset by sending an address of all zeros (00000000). this may be used to allow inter-operation with other devices sharing the l3clk and l3data lines (e.g. saa7345 cd decoder). d ata mode in data mode, bytes of data are clocked into (e.g. control) or out of (e.g. status) the slave. a single byte transfer is shown in fig.9. a two byte transfer is shown in fig.10, between bytes there must be a pause during which the clock remains high. msb lsb l3 operation mode function 0010 0000 wdat extended settings 0010 0001 rdat allocation information 0010 0010 wcmd settings 0010 0011 rstat status/peak read h alt mode halt mode consists of pulling l3mode low after sending data. it is used for marking the end of a data transfer mode which does not have an internal bit counter. saa2013 interface modes the saa2013 may be used to read and write from or to saa2003. information is transferred via a set of transit registers within saa2013. d ecode operation during decode, the saa2013 does not perform allocation. therefore no allocation and scale factor indices are sent to saa2003. settings and extended settings may still be sent to saa2003, and saa2013 monitors the status of the codec by reading status from it after every occurrence of fsync. peak level data can also be transferred from saa2003. e ncode operation in encode, the same information may be sent as for decode, and in addition, allocation/scale factor indices are sent to the codec by saa2013. the interface modes are shown in table 5.
may 1994 13 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 table 5 interface modes. mode address interface mode length (bits) direction bit 1 bit 0 decode 0 0 extended settings 8 microcontroller to saa2003 01 --- 1 0 settings 16 microcontroller to saa2003 1 1 status/peak 16 or 48 saa2003 to microcontroller encode 0 0 extended settings 8 microcontroller to saa2003 0 1 allocation/scale 48 16 saa2013 to saa2003 1 0 settings 16 microcontroller to saa2003 1 1 status/peak 16 or 48 saa2003 to microcontroller p riority each type of transfer has a priority. the priorities are: 1. allocation/scale/settings (highest priority). 2. status read. 3. peak read. 4. extended settings (lowest priority). a llocation and scale factor transfer the allocation and scale factor information sent from saa2013 to saa2003 during encode has the highest priority. the other types of transfer interleaved with the allocation/scale information. s ettings transfer this is a 16-bit transfer. the microcontroller sends settings to saa2003. saa2013 only transfers these without taking notice of the contents. in encode, the settings are held in the transit registers, and sent next time that allocation is being sent. in decode, settings are sent as soon as possible subject to the rtrc flag from saa2003. before sending settings the microcontroller should read the status of saa2013 to examine the ready-to-receive bit settings (rtrs). after the settings have been received by saa2013, rtrs will be made logic 0, until the settings have been sent to saa2003. only after rtrs is logic 1 again may the microcontroller send new settings. s tatus read status and peak information may be read from saa2003 by the microcontroller. the status bits are defined in table 6. table 6 status bits. bit name function valid in b15 to b12 bit rate index bit rate indication encode/decode b11 and b10 sample frequency indication 44.1, 48, 32 khz indication encode/decode b9 rtrs (settings) 1 = ready; 0 = not ready encode/decode b8 rtre (external settings) 1 = ready; 0 = not ready encode/decode b7 and b6 mode sub-band signal mode identi?cation encode/decode b5 sync synchronization indication encode/decode b4 clkok 1 = ok; 0 = not ok encode/decode b3 and b2 tr0 and tr1 transparent bits encode/decode b1 and b0 emphasis emphasis indication encode/decode
may 1994 14 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 since the two bytes of status information are sampled separately, the bytes may result from different sub-band frames. the only valid bit rate code for the saa2013 is 1100. the sample frequency indication is shown in table 7. table 7 sample frequency indication. ready-to-receive s or e indicates whether the saa2013 is ready-to-receive new settings or extended settings from the microcontroller. this should be checked before sending new information. for details of the mode, sync, clkok and transparent bits, refer to the saa2003 data sheet . the emphasis indication can be used to apply the correct de-emphasis. in encode saa2013 will correct the calculated allocation if 50 15 m s emphasis is applied. when ccitt j.17 emphasis is applied, the bit allocation remains the same as when no emphasis is applied. the 2 bytes of the status are sampled at different moments. so the information may not result from the same sub-band frame. when making repeated status reads (for instance reading the rtrs/rtre flags before sending settings or extended settings), the microcontroller must send an address before each status read, to ensure that the byte counter in the interface is reset to logic 0. if this is not done, then the peak data will be read. conversely, it is important not to send a new address after a status read if the peak data is required. p eak read peak information is read by clocking a further 4 bytes of data after a status read. the data format is shown in figs 11 and 12. bits b17 to b31 contain a 15-bit unsigned peak, lsb first, channel indicated by bit b16. bits b33 to b47 contain a 15-bit unsigned peak, channel indicated by bit b32. the peak data is delayed by 1 read period. if for example the microcontroller reads peak level data every 50 ms, the peak data sourced by saa2013 will be 50 ms old. also it bit 11 bit 10 sample frequency 0 0 44.1 khz; default 0 1 48.0 khz 1 0 32.0 khz 1 1 do not use is possible that peak data may contain an additional delay of 1 column (667 m s minimum at 48 khz, 1 ms maximum at 32 khz). if the microcontroller attempts to read peak level data with a delay of less than 1 column, the peak level data from the previous reading will be repeated. normally the microcontroller should allow at least 1 ms between reads. there is also a delay required between peak data words (fig.13). if the saa2013 does not have peak data available (for instance the microcontroller attempts two reads in very quick succession), it will return all peak data bits set to logic 0. the microcontroller can detect if valid peak data has been returned by inspecting bits t16 and t32. if both bits are set to logic 0 the data is not valid. handbook, halfpage 00100011 status msb peak byte 1 peak byte 3 status lsb peak byte 0 peak byte 2 msb lsb mgb364 fig.11 peak level read format; saa2013 to microcontroller. handbook, halfpage msb lsb 16 15-bit peak channel indicator bits 17 to 31 msb lsb 32 15-bit peak channel indicator bits 33 to 47 mgb365 fig.12 peak level format.
may 1994 15 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 e xtended settings this is a single byte transfer, valid during decode and encode. the sequence of operations is: 1. microcontroller reads status from saa2013, waiting for the flag rtre to be set. 2. when rtre is logic 1, the microcontroller writes address bit 0 is logic 0, bit 1 is logic 0. 3. one byte of extended settings is clocked into the transit register (saa2013). 4. when it is possible (i.e. subject to rtrc being high, and assuming that allocation or status is not waiting), the byte is transferred from the transit register to the saa2003. handbook, full pagewidth l3modec mgb366 status bytes peak 1 halt peak 2 15.625 s m fig.13 peak data timing. fig.14 l3 interface timing; saa2013 to saa2003 (address mode). handbook, full pagewidth t d3 t d4 t d5 t d2 t h1 l3modec l3clkc l3datac (adas-sfc) mgb367 cl t ch t t d1 t h2
may 1994 16 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 h andbook, full pagewidth t d3 t d4 t d5 t h2 t d2 t h3 l3modec l3clkc mgb368 cl t ch t t d1 t h1 t su1 l3datac (adas-sfc) l3datac sfc-adas) fig.15 l3 interface timing; saa2013 to saa2003 (data mode). fig.16 l3 interface timing; microcontroller to saa2013 (address mode). handbook, full pagewidth l3modem l3clkm l3datam (microcontroller- adas) mgb369 cl t ch t t d1 t h1 t su1 t h2
may 1994 17 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 handbook, full pagewidth t d3 t d4 t d5 t d2 t h3 l3modem l3clkcm mgb370 cl t ch t t d1 t h1 t su1 l3datam (adas- microcontroller) l3datam (microcontroller- adas) t h2 fig.17 l3 interface timing; microcontroller to saa2013 (data mode). fig.18 l3 interface timing; microcontroller to saa2013 and saa2013 to saa2003 (halt mode). handbook, full pagewidth l3modem/ l3modec l3clkm/ l3clkc l3data/ l3datac (output) mgb371 t d5 t h2 t d2 t d1 t l
may 1994 18 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 handbook, full pagewidth cl clk24 t f t r t ch t t mgb372 c24 fig.19 input timing clk24. fig.20 input signal timing for fsync, freset, fdir, fdws, l3modem, l3clkm, l3datam and l3datac. handbook, full pagewidth clk24 data t , t f r t h t su mgb373
may 1994 19 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 fig.21 output signal timing fdao. handbook, full pagewidth fs256 fdao t h t d mgb374 fig.22 filtered data interface timing. handbook, full pagewidth t d3 t d4 fdcl cl t ch t mgb375 t c fdao (fdai) fdai, fdws t h1 t su1
may 1994 20 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 current consumption the typical current consumption is shown in fig.23. fig.23 typical current consumption. handbook, halfpage 234 6 10 0 8 mbd697 5 6 4 2 v (v) dd i dd (ma) t amb =25 c. limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 2. equivalent to discharging a 200 pf capacitor through a 0 w series resistor. symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +6.5 v v i input voltage - 0.5 v dd + 0.5 v i i input current - 20 ma v o output voltage - 0.5 +6.5 v i o output current - 20 ma t stg storage temperature - 65 +150 c t amb operating ambient temperature - 40 +85 c v es electrostatic handling human body model (hbm) note 1 - 2000 +2000 v machine model (mm) note 2 - 200 +200 v
may 1994 21 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 characteristics v dd = 2.7 to 5.5 v; v ss = 0 v;t amb = - 40 to 85 c; unless otherwise speci?ed; i ol and i oh derated by 75% for v dd < 4.5 v. symbol parameter conditions min. typ. max. unit supply v dd supply voltage 2.7 5.0 5.5 v i dd supply current v dd = 3.0 v 4 5 6 ma v dd = 5.0 v 7 10 12 ma i stb standby current v dd = 5.0 v -- 400 m a inputs v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current v i =0tov dd - 10 - +10 m a c i input capacitance -- 10 pf outputs v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 30 pf inputs/outputs v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li 3-state leakage current v i =0tov dd - 10 - +10 m a c i input capacitance -- 10 pf v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 30 pf clock input clk24 f i input frequency see fig.19 - 24.576 - mhz t r rise time -- 7ns t f fall time -- 7ns t ch high time 10 -- ns t cl low time 10 -- ns clock input fs256 f i input frequency f s =48khz - 12.288 - mhz f s = 44.1 khz - 11.2896 - mhz f s =32khz - 8.192 - mhz t r rise time -- 7ns t f fall time -- 7ns t ch high time 35 -- ns t cl low time 35 -- ns
may 1994 22 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 inputs fsync, freset, fdir, fdws, l3modem, l3clkm, l3datam and l3datac; referenced to clk24 rising edge; see fig.20; sleep = reset = por = logic 0 t su set-up time 15 -- ns t h hold time 20 -- ns t r rise time -- 200 ns t f fall time -- 200 ns inputs fdai, fdcl, fdws, freset and fdir; referenced to fs256 rising edge; sleep = reset = por = logic 0 t su set-up time 15 -- ns t h hold time 20 -- ns t r rise time -- 200 ns t f fall time -- 200 ns output fdao; referenced to fs256 rising edge; see fig.21; sleep = reset = por = logic 0 t h hold time c l = 7.5 pf 0 -- ns t d delay time c l =30pf -- 30 ns t d3 output delay time after fdcl high see fig.22 2t c256 - 10 (1) -- ns t d4 output delay time after fdcl high see fig.22 -- 3t c256 +60 (1) ns input fdcl; see fig.22 t c fdcl period 280 4t c256 (1) - ns t ch fdcl high time t c256 +35 (1) -- ns t cl fdcl low time t c256 +35 (1) -- ns inputs fdai and fdws; see fig.22 t su1 set-up time before fdcl high 3t c256 +60 (1) -- ns t h1 hold time after fdcl high t c256 +20 (1) -- ns input freset; see fig.4 t h freset high time 1280 -- ns t su fdir set-up time before freset low 0 210 - ns t h fdir hold time after freset low 9t c24 (2) 370 - ns sleep and reset timing; see fig.5; lowpwr = logic 1 t h reset hold time after sleep low 5t c24 (2) 210 - ns t d clk24 disable after sleep high 9t c24 (2) 370 - ns symbol parameter conditions min. typ. max. unit
may 1994 23 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 l3 interface timing; microcontroller to saa2013 a ddress mode ; see f ig .16 t d1 l3modem low to l3clkm low 190 -- ns t ch l3clkm high time 250 -- ns t cl l3clkm low time 250 -- ns t su1 l3datam input set-up time before l3clkm high 190 -- ns t h1 l3datam input hold time after l3clkm high 30 -- ns t h2 l3clkm high before l3modem high 190 -- ns d ata mode ; see f ig .17 t d1 l3modem high to l3clkm low delay time 190 -- ns t ch l3clkm high time 250 -- ns t cl l3clkm low time 250 -- ns t su1 l3datam input set-up time before l3clkm high 190 -- ns t h1 l3datam input hold time after l3clkm high 30 -- ns t h2 l3clkm high before l3modem low 190 -- ns t d3 l3modem high to l3datam output valid -- 380 ns t h3 l3datam output hold time after l3clkm high 120 -- ns t d4 l3clkm high to l3datam output valid delay time -- 360 ns between bits 7 and 8; no halt mode used -- 530 ns t d2 l3modem high to l3datam output enabled delay time 0 - 50 ns t d5 l3modem low to l3datam output disabled delay time 0 - 50 ns symbol parameter conditions min. typ. max. unit
may 1994 24 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 h alt mode ; see f ig .18 t l l3modem low time 190 -- ns t d1 l3modem high to l3clkm high delay time 190 -- ns t h2 l3clkm high before l3modem low 190 -- ns t d2 l3modem high to l3datam output enabled delay time 0 - 50 ns t d5 l3modem low to l3datam output disabled delay time 0 - 50 ns l3 interface timing; saa2013 to saa2003 a ddress mode ; see f ig .14 t d1 l3modec low to l3clkc low delay time 190 -- ns t ch l3clkc high time 210 -- ns t cl l3clkc low time 210 -- ns t h2 l3clkc high time before l3modec high 190 -- ns t d3 l3modec low to l3datac output valid delay time -- 380 ns t h1 l3datac output hold time after l3clkc high 120 -- ns t d4 l3clkc high to l3datac output valid delay time -- 360 ns t d2 l3modec low to l3datac output enabled delay time 0 - 50 ns t d5 l3modec high to l3datac output disabled delay time 0 - 50 ns symbol parameter conditions min. typ. max. unit
may 1994 25 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 notes 1. t c256 is a clock period of fs256. 2. t c24 is a clock period of clk24. d ata mode ; see f ig .15 t d1 l3modec high to l3clkc low 190 -- ns t ch l3clkc high time 210 -- ns t cl l3clkc low time 210 -- ns t su1 l3datac input set-up time before l3clkc high 100 -- ns t h1 l3datac input hold time after l3clkc high 30 -- ns t h2 l3clkc high time before l3modec low 190 -- ns t d3 l3modec high to l3datac output valid -- 380 ns t h3 l3datac output hold time after l3clkc high 120 -- ns t d4 l3clkc high to l3datac output valid -- 360 ns between bits 7 and 8; no halt mode used -- 530 ns h alt mode ; see f ig .18 t l l3modec low time 190 -- ns t d1 l3modec high to l3clkc high delay time 190 -- ns t h2 l3clkc high time before l3modec low 190 -- ns l3 interface delays in bypassed mode; lowpwr = logic 1 t pd1 propagation delay from l3modem to l3modec; l3datam to l3datac; l3clkm to l3clkc -- 35 ns t pd2 propagation delay from l3datam to l3datac; l3clkm to l3clkc - 20 - +4 ns t pd3 propagation delay from l3datam to l3datac; l3modem to l3modec - 20 - +4 ns symbol parameter conditions min. typ. max. unit
may 1994 26 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 package outline handbook, full pagewidth x a b 10.1 9.9 12.9 12.3 0.15 m b 0.40 0.20 pin 1 index 1 44 34 33 23 22 11 0.40 0.20 0.15 m a 0.8 12 0.8 10.1 9.9 12.9 12.3 s 0.1 s seating plane 1.2 0.8 (4x) 1.2 0.8 (4x) 0.95 0.55 mbb944 - 2 detail x 0.85 0.75 0.25 0.14 2.10 1.70 0 to 10 o 1.85 1.65 0.25 0.05 fig.24 plastic quad flat-pack, 44-pin (short) (qfp44sl). dimensions in mm.
may 1994 27 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 soldering plastic quad ?at-packs b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
may 1994 28 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. the digital compact cassette logo is a registered trade mark of philips electronics n.v.
may 1994 29 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 notes
may 1994 30 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 notes
may 1994 31 philips semiconductors preliminary speci?cation adaptive allocation and scaling for pasc coding in dcc systems saa2013 notes
philips semiconductors philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970). tel. (011)821-2327, fax. (011)829-1849 canada: integrated circuits: tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 601 milner ave, scarborough, ontario, m1b 1m8, tel. (0416)292 5161 ext. 2336, fax. (0416)292 4477 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (9)0-50261, fax. (9)0-520971 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: philips components ub der philips g.m.b.h., p.o. box 10 63 23, 20043 hamburg, tel. (040)3296-0, fax. (040)3296 213. greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: philips hong kong ltd., components div., 6/f philips ind. bldg., 24-28 kung yip st., kwai chung, n.t., tel. (852)424 5121, fax. (852)428 6729 india: philips india ltd, components dept, shivsagar estate, a block , dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)640 000, fax. (01)640 200 italy: philips components s.r.l., viale f. testi, 327, 20162 milano, tel. (02)6752.3302, fax. (02)6752 3300. japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5028, fax. (03)3740 0580 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: philips components, 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546. philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)14163160/4163333, fax. (01)14163174/4163366. singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., components division, 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382. thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319. turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 2770, fax. (0212)269 3094 united kingdom: philips semiconductors limited, p.o. box 65, philips house, torrington place, london, wc1e 7hd, tel. (071)436 41 44, fax. (071)323 03 42 united states: integrated circuits: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 2001 west blue heron blvd., p.o. box 10330, riviera beach, florida 33404, tel. (800)447-3762 and (407)881-3200, fax. (407)881-3300 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building baf-1, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd31 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 513061/1500/01/pp32 date of release: may 1994 document order number: 9397 731 90011

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